Variation-Tolerant and Voltage-Scalable Integrated Circuits Design

Ultra-low-voltage (ULV) operation where the supply voltage of the digital computing hardware is scaled down to the level near or below transistor threshold voltage (e.g. 300-500mV) is a key technique to achieve high computing energy efficiency. It has enabled many new exciting applications in the field of Internet of Things (IoT) devices and energy-constrained applications such as medical implants, environment sensors, and micro-robots. Ultra-low-voltage (ULV) operation is also commonly used with the emerging architectures that are often non Von-Neumann style to empower energy-efficient cognitive computing. One the biggest challenge in realizing ULV design is the large circuit delay variability. To guarantee functionality in the worst-case process, voltage, and temperature (PVT) condition, the traditional safety margin approach requires operating at a slower clock frequency or higher supply voltage which significantly limits the achievable energy efficiency of the hardware. To fully claim the energy efficiency of ULV, the large circuit delay variation needs to be adaptively handled. However, the existing adaptive techniques that are optimized for nominal supply voltage operation and traditional Von-Neumann architectures become inefficient for ULV designs and emerging architectures. This thesis presents adaptive techniques based on timing error detection and correction (EDAC) that are more suitable for the energy-constrained ULV designs and the emerging architectures. The proposed techniques are demonstrated in three test chips: (1) R-Processor: A 0.4V resilient processor with a voltage-scalable and low-overhead in-situ EDAC technique. It achieves 38% energy efficiency improvement or 2.3X throughput improvement as compared to the traditional safety margin approach. (2) A 450mV timing-margin-free waveform sorter for brain computer interface (BCI) microsystem. It achieves 49.3% higher energy efficiency and 35.6% higher throughput than the traditional safety margin approach. (3) Ultra-low-power and robust power-management system which consists of a microprocessor employing ULV EDAC, 63-ratio integrated switched-capacitor DC-DC converter, and a fully-digital error based regulation controller. In this thesis, we also explore circuits for emerging techniques. The first is temperature sensors for dynamic-thermal-management (DTM). The modern high-performance microprocessors suffer from ever-increasing power densities which has led to reliability concerns and increased cooling costs from excessive heat. In order to monitor and manage the thermal behavior, DTM techniques embed multiple temperature sensors and use its information. The size, accuracy, and voltage-scalability of the sensor are critical for the performance of DTM. Therefore, we propose a temperature sensor that directly senses transistor threshold voltage and the test chip demonstrates 9X smaller area, 3X higher accuracy, and 200mV lower voltage scalability (down to 400mV) than the previous state-of-art. Another area of exploration is interconnect design for ultra-dynamic-voltage-scaling (UDVS) systems. UDVS has been proposed for applications that require both high performance and high energy efficiency. UDVS can provide peak performance with nominal supply voltage when work load is high. When work load is moderate or low, UDVS systems can switch to ULV operation for higher energy efficiency. One of the critical challenges for developing UDVS systems is the inflexibility in various circuit fabrics that are often optimized for a single supply voltage. One critical example is conventional repeater based long interconnects which suffers from non-optimal performance and energy efficiency in UDVS systems. Therefore, in this thesis, we propose a reconfigurable interconnect design based on regenerators and demonstrate near optimal performance and energy efficiency across the supply voltage of 0.3V and 1V

A Sub-50 µm2, Voltage-Scalable, Digital-Standard-Cell-Compatible Thermal Sensor Frontend for On-Chip Thermal Monitoring

This paper presents an on-chip temperature sensor circuit for dynamic thermal management in VLSI systems. The sensor directly senses the threshold voltage that contains temperature information using a single PMOS device. This simple structure enables the sensor to achieve an ultra-compact footprint. The sensor also exhibits high accuracy and voltage-scalability down to 0.4 V, allowing the sensor to be used in dynamic voltage frequency scaling systems without requiring extra power distribution or regulation. The compact footprint and voltage scalability enables our proposed sensor to be implemented in a digital standard-cell format, allowing aggressive sensor placement very close to target hotspots in digital blocks. The proposed sensor frontend prototyped in a 65 nm CMOS technology has a footprint of 30.1 µm2, 3σ-error of ±1.1 °C across 0 to 100 °C after one temperature point calibration, marking a significant improvement over existing sensors designed for dynamic thermal management in VLSI systems

Targeted Hyaluronate - Hollow Gold Nanosphere Conjugate for Anti-Obesity Photothermal Lipolysis

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Automated Data Check and Calibration System using Matrix Switch Prototype With Small Change of Line-Resistance

In this paper, the hardware performance of a matrix switch prototype with small resistance deviation of each route and an automated data check and calibration system are described. The matrix consists of 12 rows and 3 columns, and the key switch connecting the rows and columns has a small on-resistance change even when the input voltage changes, so the matrix can keep the resistance deviation of each route small. Data check and calibration of circuits that are sensitive to errors due to lead-wires can also be automated with this matrix system to save time and reduce human error.International Foundation for TelemeteringProceedings from the International Telemetering Conference are made available by the International Foundation for Telemetering and the University of Arizona Libraries. Visit https://telemetry.org/contact-us/ if you have questions about items in this collection

Analysis of Energy Consumption of Novel Re-Liquefaction System Integrated with Fuel Supply System (FSS) for LPG-Fuelled LPG Carrier to Conventional Systems

This study analysed a novel re-liquefaction system integrated with a fuel supply system (FSS) for an LPG carrier to conventional systems. The re-liquefaction system and FSS were installed independently in a conventional LPG carrier, while those systems were combined in the novel system. The condensed LPG in the re-liquefaction system was directly transferred to the FSS without the cooling and expansion process in the novel system. 84,000 m3 LPG carrier equipped with a 10 MW engine at normal continuous rating (NCR) was selected as a target ship. Aspen HYSYS ver.12.1 was employed for process simulation. The results showed that the energy consumption for the novel system was reduced by 38%. The energy for re-liquefaction was decreased because the flow rate recirculated was decreased, and the energy for FSS was reduced as the temperature of the stream supplied to the FSS was relatively high in the novel system. A sensitivity analysis was conducted to investigate the effect of the parameters on the results. The investigated parameters were LPG compositions, seawater temperature, compressor efficiency, and pump efficiency. The energy consumption for the system was significantly different depending on the LPG composition, and the energy consumption was changed by 2.5% for conventional systems and 0.9% for the novel systems with the variation of 4 °C seawater temperature. The energy for the novel system was reduced by 2.8% for conventional systems and 2.3% for the novel systems with the 5% increment of compressor efficiency, whereas pump efficiency had little effect on the results

Analysis of Energy Consumption of Novel Re-Liquefaction System Integrated with Fuel Supply System (FSS) for LPG-Fuelled LPG Carrier to Conventional Systems

This study analysed a novel re-liquefaction system integrated with a fuel supply system (FSS) for an LPG carrier to conventional systems. The re-liquefaction system and FSS were installed independently in a conventional LPG carrier, while those systems were combined in the novel system. The condensed LPG in the re-liquefaction system was directly transferred to the FSS without the cooling and expansion process in the novel system. 84,000 m3 LPG carrier equipped with a 10 MW engine at normal continuous rating (NCR) was selected as a target ship. Aspen HYSYS ver.12.1 was employed for process simulation. The results showed that the energy consumption for the novel system was reduced by 38%. The energy for re-liquefaction was decreased because the flow rate recirculated was decreased, and the energy for FSS was reduced as the temperature of the stream supplied to the FSS was relatively high in the novel system. A sensitivity analysis was conducted to investigate the effect of the parameters on the results. The investigated parameters were LPG compositions, seawater temperature, compressor efficiency, and pump efficiency. The energy consumption for the system was significantly different depending on the LPG composition, and the energy consumption was changed by 2.5% for conventional systems and 0.9% for the novel systems with the variation of 4 °C seawater temperature. The energy for the novel system was reduced by 2.8% for conventional systems and 2.3% for the novel systems with the 5% increment of compressor efficiency, whereas pump efficiency had little effect on the results